1.6GHZ，2W集成式调谐射频式接收功率放大器的设计外文翻译 本文简介：
Designofintegrated1.6GHz,2WtunedRFpoweramplifierAbstract：ThispaperdescribesthedesignofanintegratedtunedpoweramplifierspecifiedtooperateatInmarsatsatel
1.6GHZ，2W集成式调谐射频式接收功率放大器的设计外文翻译 本文内容：
Design
of
integrated
1.6
GHz,
2
W
tuned
RF
power
amplifier
Abstract：
This
paper
describes
the
design
of
an
integrated
tuned
power
amplifier
specified
to
operate
at
Inmarsat
satellite
uplink
frequencies
from
1626.5
to
1660.5
MHz.The
basic
topology
of
the
amplifier
lies
on
the
parallel
tuned
inverse
class
E
amplifier
that
is
modified
by
placing
the
DC-blocking
capacitor
into
a
new
position
and
by
adjusting
the
size
of
the
capacitor
to
improve
stability
below
the
desired
band.
Further,
the
new
positioning
reduces
losses
between
drain
and
load.
The
high
currents
flowing
in
the
circuit
made
it
necessary
to
use
wide
inductor
width
and
high-Q
finger
capacitors
in
the
on-chip
resonator.
The
amplifier
was
implemented
as
a
Gallium
Arsenide
(GaAs)
integrated
circuit
(IC)
that
delivered
2
W
of
output
power
while
the
drain
efficiency
was
ca.
56%.Measurements
included
source
and
load
pulls
to
further
improve
the
performance
of
the
amplifier
and
to
investigate
the
stability
at
small
input
drive
levels.
Keywords:
Inverse
class
E?Power
amplifier.Self-oscillation?
Bias
network
1
Introduction
The
usability
of
traditional
linear
amplifiers
in
today’s
high
power
communications
systems
is
limited
due
to
their
low
efficiency.
This
fact
has
driven
the
interest
of
research
towards
more
efficient
amplifiers
such
as
class
E
[1–3]
and
inverse
class
E
[4].
Also,
the
demand
of
higher
output
power
means
higher
peak
currents
and
voltages
in
the
drain
or
collector
circuits.
This
creates
high
requirements
for
both
maximum
breakdown
values
of
the
transistor
and
to
the
passive
circuitry
of
the
monolithic
microwave
integrated
circuit
(MMIC).
The
effect
of
limited
conductivity
and
limited
capability
to
cope
with
heat
can
be
minimized
through
careful
design
of
MMIC.
Further,
emerging
transistor
technologies
seem
to
withstand
larger
current
densities
and
peak
voltages
[5],
and
therefore,
the
choice
of
technology
is
increasingly
important
when
designing
high
power
devices.
The
aim
of
this
paper
is
to
show
experiences
related
to
the
design
of
switching
high
power
radio
frequency(RF)
amplifiers
(PA)
with
integrated
output
pulse
shaping.
In
the
second
chapter
the
introduction
to
class
E
and
inverse
class
E
operation
is
revisited
and
the
differences
between
the
two
topologies
are
reviewed.The
third
chapter
describes
the
design
of
the
input
and
output
circuitry,
stabilizing
circuits
and
provides
some
tips
to
minimize
timing
differences
at
the
input
of
a
multi-finger
transistor.
The
fourth
chapter
shows
the
final
schematic
and
a
photo
of
the
implemented
chip.
The
measured
performance
is
reported
in
chapter
five
by
using
both
basic
single
tone
measurement
equipment
and
a
modern
load
pull
system
using
multi-purpose
tuners(MPT).
The
last
section
provides
a
summary
of
the
article
and
discussion
of
the
issues
related
to
stabilizing
circuits.2
Class
E
and
inverse
class
E
amplifiersClass
E
and
inverse
class
E
are
regarded
as
switching
amplifiers.
Ideally,
in
both
of
them
the
transistor
is
driven
either
on
or
off
and
this
switching
operation
produces
a
series
of
voltage
and
current
pulses
to
the
output.
These
pulses
are
phase
shifted
and
therefore
do
not
overlap
with
each
other.
Ideal
non-overlap
causes
the
transistor
to
operate
with
drain
efficiency
of
100%.
Classical
class
E
drain
waveforms,
normalized
to
DC
values
of
supply
current
and
voltage,
are
shown
in
Fig.1.The
solid
line
is
normalized
drain
current
waveform
and
the
dashed
line
is
normalized
drain
voltage.
The
requirement
for
optimal
operation
in
class
E
is
zero
voltage
switching
(ZVS),
where
the
drain
voltage
and
its
derivative
goes
to
zero
just
before
the
transistor
starts
to
conduct.
In
inverse
class
E
the
waveforms
have
swapped
places
so
that
the
solid
line
waveform
in
Fig.1
is
the
drain
voltage
and
the
dashed
line
is
the
drain
current.
The
optimal
operation
is
also
changed
to
zero-current
switching
(ZCS),
where
the
current
and
its
derivative
goes
smoothly
to
zero
before
the
transistor
enters
nonconducting
phase.
Advantages
of
inverse
class
E
over
classical
realization
are
that
the
drain
peak
voltages
are
lower
than
in
classical
class
E
and
the
inductance
values
in
the
output
circuitry
are
smaller,
which
can
save
area
in
a
MMIC
chip
implementation
and
can
usually
give
smaller
electrical
series
resistance
(ESR)
[4].
Also,
the
possibility
to
accommondate
series
inductance
as
a
part
of
resonating
circuitry
is
useful,
since
the
parasitic
reactances
can
cause
undamped
resonances
to
drain
waveforms
[6,
7].
These
advantages
were
the
reasons
for
choosing
inverse
class
E
topology
as
a
starting
point
for
our
investigation.
However,
the
tuned
implementation
is
not
traditional
inverse
class
E,
although
it
has
similar
pulsed
operation.3
Design
of
tuned
power
amplifier
3.1
GaAs
IC
process
The
IC
process
used
is
a
Triquint
Semiconductor’s
pseudomorphic
high
electron
mobility
transistor
(pHEMT)
process
named
TQPED.
The
process
utilizes
both
enhancement
and
depletion
mode
field
effect
transistors
(FETs)
with
0.5lm
length
optical
lithography
gates,
but
in
our
case
we
used
only
depletion
mode
transistors.
The
available
depletion
mode
transistors
have
a
transition
frequency
(Ft)
of
27
GHz,
drain-gate
breakdown
voltage
of15
V
and
nominal
pinch-off
point
of-0.8
V.
Transistors
models
used
are
TOM3
FET
models.
There
are
several
other
features
in
the
process:
nichrome
(NiCr)
resistors
for
precision
and
bulk
for
high
value
resistors,
high
value
Metal–Insulator–Metal
(MIM)
capacitors,
1
local
and
2thick
global
metal
layers
[8].
3.2
Design
of
the
resonator
The
difference
between
the
original
inverse
class
E
in
Fig.2and
the
final
tuned
topology
used
in
our
design,shown
in
Fig.3,
is
the
location
of
blocking
capacitor
Cs.The
original
placing
in
Fig.2provides
the
DC-blocking
to
two
directions:
to
the
output
(load)
and,
more
important,
it
blocks
the
direct
DC-current
path
through
Lp
to
ground.In
our
case
the
blocking
capacitor
is
underneath
the
resonating
circuit
as
shown
in
Fig.3,
where
the
Cs
obstructs
the
flow
of
DC-current
through
Lp
to
ground,
but
not
to
the
output
(load).
There
is
a
direct
way
for
fundamental
current
to
flow
to
the
output,
without
passing
any
blocking
capacitor.
The
DC
blocking
capacitor
can
now
be
made
significantly
smaller.
In
our
case
the
reduction
was
from100
pF
to
less
than
50
pF,
which
means
savings
in
chip
area
and
as
a
secondary
effect,
the
ability
to
tune
a
stabilizing
trap
to
wanted
frequency
(more
in
chapter
3.2)
while
maintaining
good
amplifier
performance.
The
design
of
the
DC-block
is
now
also
slightly
easier,
since
peak
current
flowing
into
the
blocking
branch
is
smaller.
Furthermore,the
ESR
between
drain
and
load
is
smaller.
The
fundamental
current
amplitudes
in
components
Cs
andLwere1.2
and
2
A,
respectively.
The
total
peak
currents
in
the
parallel
resonator
structure
can
be
seen
in
Fig.3.
The
traditional
inverse
class
E
dimensioning
[4]
for1.6
GHz
and
Pout=3
W
results
in
large
chip
area,
as
due
to
high
Q
=10
the
capacitor
Ctot
is
large
(63.5
pF)
and—due
to
high
peak
currents
(ca.
6
A)—the
inductor
gets
physically
huge.
To
get
reasonable
on-chip
component
values
the
design
was
gradually
deviated
from
the
design
procedure
in
[4]
by
shifting
it
towards
lower
load
resistance
and
Q
value,
and
increasing
the
resonance
frequency.
This
ended
up
in
a
dimensioning
that
provides
clean,
nonoverlapping
current
and
voltage
pulses,
reasonable
size
passives,
but
which
is
eventually
closer
to
class
C–E
fundamental
load
[9]
than
to
original
inverse
class
E.
The
final
component
values
of
the
simulation
with
discrete
component
models
and
an
off-chip
low-pass
impedance
matching
network
to
50Ω
resulted
in
the
following
dimensioning:resistive
load
4Ω,Ctot
=30
pF,Lp=0:22
nH,and
L
so
small
it
could
be
omitted
from
the
final
design.Cs
could
be
reduced
down
to
50
pF
without
affecting
the
overall
performance,
and
it
can
be
used
to
tune
a
stabilizing
below
the-carrier
notch,
as
shown
later
in
Fig.
8.
The
overall
simulation
results
with
a
large
switching
transistor
(12parallel
transistors
with
18×50μm/0.5μm
fingers)
estimated
5.6
W
output
power
with
72%
drain
efficiency.
The
challenge
was
now
to
maintain
as
good
output
power
and
efficiency
while
replacing
the
ideal
circuit
components
with
process
design
kit
(PDK)
components
and
while
adding
some
stabilizing
circuits
to
the
topology.Next
design
problem
came
with
the
physical
design
of
the
inductor.
Despite
the
lowered
Q
value
the
current
amplitude
was
still
so
high
(4.2
A
peak)
that
ca.
200lmwide
metal
line
was
needed
for
the
inductor,
and
to
keep
the
center
of
the
3/4-turn
inductor
open
it
could
not
be
made
physically
smaller
than
0.4
nH.
Hence,
the
capacitance
Ctot
and
Q
value
were
further
reduced
a
bit,
and
to
reduce
resistive
losses
the
capacitance
Ctot
was
split
into
12parallel
high-Q
capacitors.
The
drawn
layout
of
the
resonator
structure
was
imported
into
2.5D
field
simulator,
and
S-parameters
were
simulated
and
compared
with
those
of
the
discrete
simulation
prototype.
The
unloaded
phase
and
magnitude
of
the
impedance
data
for
comparisons
from
S-parameter
simulations
are
shown
in
Figs.4and5.
The
phase
and
magnitude
data
of
a
distributed
resonator
is
marked
with
a
dashed
line
in
both
figures.
The
phases
and
magnitudes
of
the
resonators
follow
almost
the
same
line.When
the
complete
amplifier
was
simulated,
the
drain
efficiency
was
about
70%
and
output
power
was
about3.4
W.
The
reduction
in
output
power
may
be
explained
by
parasitic
resistances
and
by
the
addition
of
stabilizing
circuits.
The
drain
efficiency
is
surprisingly
good
despite
the
somewhat
lowered
Q
and
empirical
output
circuit
design.The
simulated
and
implemented
distributed
resonator
is
shown
in
Fig.6.3.3
Stabilizing
the
amplifierThe
amplifier
showed
a
tendency
of
instability
during
large-signal
S-parameter
(LSSP)
simulations.
In
the
end,stability
had
to
be
evaluated
through
LSSP-based
stability
circles
since
unconditional
stability
(K>1)
could
not
be
achieved
without
heavy
losses.
Stability
circles
were
drawn
throughout
a
frequency
range
of
0.5–5
GHz.
After
several
simulations,
a
variety
of
stabilizing
circuits
had
to
be
used
to
compensate
ringing
behaviour.First
the
discrete
capacitor
Cs
was
tuned
to
50
pF
to
generate
a
trap
in
the
output
resonator
at
about
1.2
GHz
frequency.
This
helped
in
achieving
stability
at
frequencies
below
the
frequency
bandas
shown
by
Rollett’s
K-factor
in
Fig.7.
The
50
pF
value
was
chosen
for
both
small
degradation
in
output
power
and
for
good
stability
performance.
The
effect
of
tuning
of
the
capacitor
Cs
is
shown
in
Fig.
8,
where
the
capacitor
is
tuned
from
30
to
70
pF.
Further,
5Ωof
series
resistance
was
added
to
three
gate
lines
as
shown
in
Fig.
9(b)
to
keep
the
amplifier
stable
with
output
standing
wave
ratio
(SWR)
range
of
4.6:1.
Also,
a
wideband
RC-sink
circuit
was
included
in
the
input
of
the
amplifier
to
reduce
the
gain
in
higher
frequencies.The
stable
output
SWR
range
increased
with
the
RC
filter
to
22.6:1.
According
to
the
simulations
the
series
resistances
caused
about
0.46
dB
gain
loss
and
the
RC
filter
again
an
additional
0.67
dB.
If
the
amplifier
had
to
be
unconditionally
stable
(K>1),
in
the
frequency
range
of
0.1
GHz
to
8.0
GHz,
the
increase
of
series
resistances
to
9Ω
would
cause
an
additional
0.40
dB
gain
loss
and
more
attenuation
to
the
drive
signal.
The
total
decrease
of
gain
due
to
stabilization
would
then
be
1.53
dB,
from
maximum
gain
of
11.36–9.83
dB.
In
the
implemented
form,
the
maximum
simulated
gain
is
10.23
dB.
3.4
Input
signal
timing
in
a
physically
large
transistorDuring
simulations
there
was
a
noticeable
phase
shift
between
extreme
fingers
of
the
wide
transistor
consisting
of12918
transistors
with
a
width
of
50lm
each.
This
phase
shift
caused
partial
overlap
between
output
pulses
and
decreased
the
drain
efficiency.
At
that
time
the
input
network
was
made
of
a
ladder-like
structure
shown
as
an
example
in
Fig.9(a).
The
distance
of
the
line
between
FETA
and
FET
B
is
close
to
1
mm,
which
as
a
pure
line
delay
would
result
in
about
20
ps
of
delay.
But
the
delay
difference
was
more
than
80
ps
and
also
the
pulse
width
of
the
input
signal
was
larger
than
predicted.
Since
the
transistors
do
not
switch
simultaneously,
they
start
to
load
each
other
and
consume
more
power.
The
reason
for
increased
delay
and
widened
pulse
width
is
the
signal
dependent
gate
capacitance
that
causes
considerable
amount
of
second
harmonic
distortion
in
the
unterminated
ladder-like
input
network
in
Fig.9(a).
where
the
signal
paths
are
almost
equal
in
length.This
improved
the
timing
behaviour
and
the
input
waveform
phasing
in
the
simulations
was
nearly
the
same.
Only
the
pulse
width
was
still
somewhat
large.
The
equal
input
routing
increased
the
drain
efficiency
of
the
amplifier
from55
to
68%.
The
effects
of
gate
capacitance
together
with
additional
solutions
to
timing
problems
have
been
published
in
[10].4
Final
circuit
The
amplifier
die
sized
1.96mm
×3.62
mm
(W×L)
was
glued
directly
to
a
6mmthick
aluminium
heat
sink.
The
gold-plated
printed
circuit
board
(PCB)
containing
output
matching
network
and
some
of
the
gate
biasing
network
was
mounted
onto
the
heat
sink.
Next
the
chip
was
wire
bonded
and
SMA
connectors
were
added
to
the
circuit.
The
final
circuit
schematic
is
shown
in
Fig.10,
where
the
dashed
line
is
used
to
separate
the
on-
and
off-chip
components.
Lower
left
side
in
the
figure
is
an
LC-matching
network
which
is
followed
by
an
RC-sink
circuit.
The
RC-circuit
increases
the
stability
of
the
amplifier
by
providing
a
wideband
loading
at
higher
frequencies.
In
the
gate
bias
circuit,
upwards
from
the
matching
circuit
is
the
parallel
RLC-circuit
that
is
a
high
impedance
at
the
operating
frequency
while
the
off-chip
parallel
RC-circuit
provides
additional
bias
resistance
in
the
low
frequencies,
thus
increasing
the
stability
of
the
amplifier.
On
the
right
side
of
the
transistor,
the
tuned
output
resonator
together
with
the
off-chip
matching
circuit
is
shown.
Drain
supply
voltage
is
directed
through
a
long
transmission
line
that
is
a
high
impedance
at
the
operation
frequency.
The
parallel
gate
RC
bias
circuit
and
output
matching
circuit
were
implemented
on
the
PCB,
which
simplified
the
implemented
chip
shown
in
Fig.
11.
Upper
left
box
(a)
is
the
LC
input
matching,
lower
left
box
(b)
is
the
RLC
bias
network
and
on
the
right
of
the
bias
is
the
box
(c)containing
the
RC-sink
circuit.
The
equal
length
input
lines
are
shown
in
the
box
(d),
where
the
added
series
resistors(5Ωeach)
show
as
wide
sections
in
between
the
equal
length
lines.
The
transistor
set
is
shown
in
box
(e)
and
it
consists
of
12
transistors
each
of
which
contain
18
fingers
with
a
width
of
50lm
each.
The
saturation
current
of
the
transistor
is
about
4
A.
On
the
right
from
the
transistor
set
there
is
the
output
path
together
with
the
parallel
resonator
in
the
box
(f).
Bonding
pads
are
below
(Gate
bias),
on
the
left
(RF
in)
and
up
(RF
out
and
drain
bias).
Two
or
three
bondwires
are
used
to
minimize
series
resistance
and
inductance
and
also
to
maximize
current
capability
of
the
wires.
4.1
The
implemented
amplifier
The
implemented
amplifier
is
shown
in
Fig.12togetherwith
a
picture
of
the
chip
layout.
The
resonator
structure
on
the
right
side
of
the
layout
is
clearly
visible
in
the
actual
chip.
The
PCB
had
to
be
drilled
open
and
the
aluminium
base
plate
machined
for
levelling
the
chip
along
the
PCB
surface.
This
way
the
bondwires
are
kept
as
short
as
possible.
The
PCB
contains
the
impedance
transforming
network
required
by
the
output
of
the
amplifier.
Further,
the
supply
is
provided
through
long
line
that
has
relatively
high
impedance
at
the
fundamental
and
has
low
resistance
atDC.
A
part
of
the
gate
biasing
network
is
also
located
in
the
PCB.
The
total
size
of
the
PCB
is
17.1
mm×37.6
mm(Width9Length).
5
Measured
performance
5.1
Measurement
setups
A
single
tone
measurement
was
used
to
measure
the
amplifier
output
power
and
efficiency.
An
IFR
2025
signal
generator
and
a
buffer
amplifier
from
Mini-Circuits
provided
the
drive
signal
level
of
25
dBm.
The
output
was
measured
with
a
Rohde
&
Schwarz
ZVA
8
vector
spectrum
analyser
(VSA).
The
load
pull
measurements
were
performed
with
Focus
Microwaves
MPT
1820
tuners
that
were
applied
both
to
the
input
and
output
of
the
amplifier.
As
a
source
was
Rohde
&Schwarz
SMU
200A
with
a
buffer
amplifier.
The
input
power
levels
were
from
15
to
25
dBm.
The
RF
input
and
output
powers
were
measured
with
Anritsu
ML2438Apower
meter
with
dual
input.
The
harmonic
content
of
the
spectrum
and
oscillation
spikes
were
measured
with
Rohde&
Schwarz
FSQ
40
VSA.
5.2
Tuning
of
the
amplifier
In
the
first
measurements
the
amplifier
did
not
meet
the
simulated
response.
Measurements
gave
only
0.96
W
of
output
power
at
1575
MHz
when
the
simulated
figures
were
3.4
W
of
output
power
and
drain
efficiency
of
70%,all
at
supply
voltage
of
5.5
V.
Our
suspicion
directed
towards
a
scribe
line
that
passed
very
close
to
the
output
resonator
structure
and
possibly
could
couple
the
output
to
the
input
of
the
amplifier.
The
scribe
line
was
cut
with
an
UV-laser
but
this
had
no
effect
to
the
frequency
response.The
measured
DC
current
of
the
amplifier
was
considerably
higher
than
simulated,
suggesting
that
the
load
impedance
of
the
switching
stage
was
too
low.
The
impedance
seen
at
the
drain
was
increased
by
replacing
a
pair
of
2.7
pF
high-Q
ceramic
capacitors
(Amplifier
A,
inTable1)
in
the
external
output
matching
network
with
one
2.9
pF
capacitor
(Amplifier
B,
in
Table1).
This
modification
increased
the
output
power
to
2
W
and
the
drain
efficiency
to
56%
at
the
frequency
of
1625
MHz.
The
output
power
and
efficiency
in
the
frequency
range
of1.5–1.7
GHz
is
shown
in
Fig.13.
The
output
power
is
maintained
within
0.53
dB
in
the
desired
frequency
range(1626.5–1660.5
MHz)
as
shown
in
Fig.
13.
Within
that
same
frequency
band
the
drain
efficiency
stays
above53%
while
the
highest
efficiency,
56%,
is
achieved
at1626
MHz.
By
adjusting
the
supply
voltage
the
efficiency
of
the
amplifier
can
be
increased
even
more,
which
can
be
seen
from
Fig.14.
Drain
efficiency
increases
steadily
when
supply
is
lowered.
At
a
supply
voltage
of
2.5
V
and
frequency
of
1625
MHz,
the
amplifier
has
a
drain
efficiency
of
65%.
This
implies
that
the
amplifier
can
maintain
an
efficient
operation
also
when
used
in
an
envelope
elimination
and
restoration
(EER)
system.
The
high
peaks
in
at
lowest
supply
voltages
in
Fig.
14are
caused
by
drive
signal
feedthrough
that
sums
into
the
output
signal.5.3
Load
pull
measurements
Measurements
were
performed
with
load
pull
system
at1.6
GHz
spot
frequency
to
several
modified
amplifiers.
The
differences
between
the
amplifiers
are
shown
in
Table1.In
the
next
chapters
we
will
mainly
concentrate
on
amplifiers
C
and
D
for
reasons
that
will
be
apparent
later
on.
Let
us
now
discuss
the
amplifier
C
which
is
very
similar
to
amplifier
B
measured
earlier.
Tuners
of
the
load
pull
system
were
connected
to
the
outputs
and
inputs
of
the
amplifier
C.
The
load
tuning
of
fundamental,
second
harmonic
and
third
harmonic
resulted
in
about
2.4
W
of
output
power
(33.8
dBm)
while
maintaining
about
57.4%
drainefficiency
at
this
peak
power
spot.The
fundamental
load
impedance
in
terms
of
power
was
at
slightly
higher
impedance
than
the
optimum
drain
efficiency
point
as
shown
in
Fig.15,
where
the
-1
dB
output
power
points
(triangles)
and-5%
unit
efficiency
points(circles)
are
shown.
The
peak
efficiency
point
in
the
figure
is
(a)
(58.6%)
and
peak
power
is
(b)
(33.9
dBm).
The
optimum
efficiency
area
is
rather
large.
Both
of
the
load
harmonics
were
even
more
relaxed,
and
differences
for
example
in
output
power
had
to
be
measured
in
tenths
of
decibels
rather
than
in
decibels.
Further,the
efficiency
differences
were
measured
in
one
or
two
percentage
units
instead
of
five
to
ten.
As
an
example,
the
third
harmonic
optimum
output
points
within
0.2
dB
from
maximum
(triangles)
and
efficiency
points
within
2%
units
from
maximum
(circles)
are
shown
in
Fig.
16.
As
it
can
beseen,
the
third
harmonic
impedance
is
not
as
critical
as
the
fundamental
tone.
The
optimum
efficiency
is
marked
with(a)
and
maximum
output
power
is
marked
with
(b).
It
should
be
noted
that
the
adjustment
of
the
third
harmonic
did
not
increase
output
power
on
the
absolute
scale
nor
the
drain
efficiency.
The
peak
output
power
value
remained
within
0.2
dB
of
the
peak
value
of
the
fundamental
load
pull
and
the
drain
efficiency
rose
from
58.6
only
to
59.8%shown
at
the
Smith
chart
point
(a)
in
Fig.16.
The
insensitivity
of
the
amplifier
to
harmonic
tuning
is
caused
by
the
long
drain
bias
line
that
is
low
impedance
at
the
second
harmonic
and
the
low
pass
matching
network
at
the
output
that
attenuates
the
third
harmonic.
5.4
Source
pull
measurements
The
source
pull
of
the
fundamental
impedance
did
increase
the
output
power
and
efficiency
of
amplifier
C
slightly.
The
optimum
drain
efficiency
(circles)
and
output
power
points(triangles)
(a)
and
(b),
respectively,
are
shown
Fig.
17.
The
power
points
are
within
the
limits
of
0.2
dB
and
efficiency
within
a
difference
of
2%
units.
The
amplifier
efficiency
rose
with
the
fundamental
source
tuning
to
62.1%
(point
a)and
the
output
to
about
2.5
W
(34.1
dBm,
point
b).
Harmonic
source
pull
measurements
showed
that
the
harmonic
impedances
were
not
as
critical
as
the
fundamental.
This
is
due
to
the
low
pass
input
matching
and
the
wideband
RC-sink
circuit.
The
RC-sink
circuit
lowers
the
calculated
magnitude
of
the
impedance
especially
at
high
frequencies,as
shown
in
Fig.18(b).
This
has
an
effect
to
both
second
and
third
harmonic
impedances.
The
magnitude
of
the
impedance
without
the
RC-sink
is
shown
as
a
reference
in
Fig.18(a).
In
both
cases
the
input
matching
circuits
were
not
included
in
the
calculations.5.5
Stability
of
the
amplifierAt
first
the
amplifier
A
did
show
some
unstable
behaviour
due
to
supply
voltage
modulation
caused
by
insufficient
bias
decoupling
at
the
drain.
The
instability
appeared
at
low
input
power
levels
as
noise
sidebands
that
lied
on
both
sides
of
fundamental
frequency.
When
input
power
was
lowered
further
on,
the
amplifier
did
break
into
full
scale
oscillation.
As
a
cure,
the
supply
impedance
was
lowered
by
a
large
number
of
decoupling
capacitors
(4
×470
pF)added
to
the
drain.
In
an
EER
application,
the
supply
modulator
will
provide
low
enough
impedance
at
the
drain.When
the
load
pull
was
done
to
the
amplifiers
A,
C
and
D,
a
spurious
oscillation
detection
was
applied
at
a
level
of-50
dBc.
With
this
setup
we
were
able
to
compare
the
sensitivity
of
different
amplifiers
to
oscillations.
We
found
out
that
the
RC-sink
circuit
used
in
amplifiers
A
and
C
indeed
improved
stability,
especially
in
the
low
input
power
levels.
Data
used
for
comparison
was
measured
from
amplifier
D,
where
the
RC-sink
was
cut
using
an
ultraviolet
laser.
The
oscillation
points
of
the
fundamental
impedance
load
pull
with
a
low
15
dBm
input
power
are
shown
in
Fig.19.
The
oscillation
sidebands
detected
are1701
and
1489
MHz.
If
we
compare
this
result
to
amplifier
A,
the
amount
of
found
oscillation
points
is
considerably
smaller
and
the
location
of
them
is
rather
tightly
spaced
in
the
low
impedance
area,
as
shown
in
Fig.
20.
The
oscillation
frequency
in
this
case
is
1568
MHz.
The
amplifier
A
and
amplifier
D
had
a
different
frequency
for
the
modulating
spurious
components:
Without
the
damping
circuit
the
modulating
spurious
was
ca.±100
MHz,
while
with
the
damper
the
modulation
appeared
at
about±30
MHz.
The
probable
reason
for
this
lies
in
different
drain
bypassing
as
the
amplifier
D
had
less
supply
capacitance
(4×470
pF
less).
The
effect
of
this
was
studied
by
simulating
from
input
to
load
transmission
(S21)
in
the
drain
bias
and
matching
network.
The
circuit
from
amplifier
D
shows
resonance
at
around
93
MHz
as
shown
in
Fig.
21(a),
while
in
the
amplifier
A
the
drain
resonance
is
at
27
MHz
frequency
as
shown
in
Fig.21(b).
As
a
reference,
a
measured
spectrum
of
amplifier
A’s
output
is
shown
in
Fig.22,
where
the
markers
one
and
four
are
at±33
MHz
distance
from
the
fundamental
frequency.
The
input
power
in
this
case
is15
dBm
and
fundamental
load
impedance
is
at
one
of
the
found
oscillation
impedances(Г=0.370,?=165.3).The
increase
of
chip
decoupling
capacitors
(4×470
pF)
in
the
case
of
amplifier
A
did
lower
the
resonance
from
around100
MHz
into
30
MHz
region.
Inside
the±30
MHz
band
there
are
also
other
oscillation
tones
which
resemble
a
quasi-periodic
solution
and
a
chaos
spectrum
combined.Examples
of
quasi-periodic
and
chaos
spectrums
are
shown
for
example
in
[11].
An
interesting
point
of
the
resonance
seen
was
that
the
large
electrolytic
capacitors
applied
to
the
bias
supply
did
not
attenuate
the
about
30
MHz
resonance,due
to
its
high
inductance.5.6
Additional
findings
Switching
amplifiers
are
dependent
on
sufficient
amount
of
gate
drive,
and
variations
in
the
drive
signal
affect
quickly
the
performance
of
the
amplifier.
In
our
case
small
variations
in
transistor
pinch-off
voltage
resulted
in
2–3
dB
differences
in
gain
between
the
amplifiers
when
bias
voltage
was
kept
constant.
Such
clear
differences
could
beseen
in
vector
network
analyser
measurements
with
a
0
dBm
input
drive.
More
constant
results
could
be
derived
by
adjusting
the
small
drain
bias
currents
to
equal
when
no
drive
signal
was
applied.
Now
the
measurements
of
gain
were
matched
within
0.8
dB.6
Summary
A
tuned
RF
power
amplifier
has
been
designed
for
operation
in
a
frequency
band
of
1.6–1.7
GHz.
The
amplifier
was
designed
empirically
to
have
non-overlapping
drain
voltage
and
current
pulses,
and
the
required
resonant
circuit
was
implemented
on-chip.
A
new
position
of
the
DC-blocking
capacitor
genereted
a
resonator
trap
that
stabilizes
the
amplifier
below
the
desired
band,
and
a
gate
RC-sink
circuit
was
used
to
stabilize
the
amplifier
at
higher
frequencies.
Further,
equal
length
input
lines
were
implemented
to
equalize
the
timing
of
gate
signals.
The
stability
of
the
amplifier
was
evaluated
through
simulations
of
large
signal
S-parameters
and
stability
circles.
Additional
resistances
together
with
an
RC-sink
circuit
had
to
be
applied
to
keep
the
stable
output
SWR
range
at
more
than
22.6:1.
The
amplifier
was
implemented
onto
a
GaAs
substrate
with
depletion
mode
high
electron
mobility
transistors
(FETs).
The
implemented
amplifier
delivers
2
W
of
output
power
while
maintaining
56%
drain
efficiency.
The
frequency
response
is
within
0.53
dB
at
a
frequency
band
of
1626.5–1660.5
MHz
while
the
drain
efficiency
stays
above
53%
in
this
desired
band.
The
amplifier
was
also
measured
with
a
load
pull
system
at
a
spot
frequency
of
1.6
GHz.
With
the
help
of
tuners
the
amplifier
achieved
about
2.5
W
of
output
power
and
62%efficiency.
Load
pull
also
revealed
the
amplifier’s
sensitivity
to
oscillations
at
small
drive
levels.
It
was
found
out
that
the
output
matching
network
has
a
low-frequency
resonance
that
might
contribute
to
the
unstable
behaviour.The
implemented
gate
sink
was
verified
to
stabilize
the
circuit.It
might
be
a
beneficial
idea
to
design
an
input
LC-trap
circuit
tuned
to
the
second
harmonic,
since
there
is
second
harmonic
content
at
the
input
which
widens
the
input
waveform
in
the
time
domain,
creating
problems
in
terms
of
efficiency
and
power.
Further,
increasing
the
third
harmonic
content
could
make
the
input
waveform
more
square-like
which
is
a
desired
feature
in
switching
amplifiers.
Acknowledgements：
This
work
has
been
supported
by
The
Academy
of
Finland,
Infotech
Oulu
Graduate
School,
TriQuint
Semiconductor
Inc.,
Nokia
Foundation,
Tauno
Tonning
Foundation,Ulla
Tuominen
Foundation
and
The
foundation
of
Riitta
and
Jorma
J.
Takanen.
My
special
thanks
to
the
personnel
of
the
Department
of
Electronics
and
Telecommunications
in
the
Norwegian
University
of
Science
and
Technology
(NTNU)
and
to
the
personnel
of
the
Micro-
and
Nanotechnology
Centre
in
the
University
of
Oulu.
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S.
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power
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MA
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F.
(1977).
Idealized
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e
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Class
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581–584).
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Hietakangas,
S.,
Rautio,
T.,
&
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T.
(2006).
1
ghz
class
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power
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polar
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24th
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Hietakangas,
S.,
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T.,
&
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(2008).
One
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Semiconductor
Inc.
(2007).TQPED
0.5
um
E/D
pHEMT
foundry
service
(2.2
edn).
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Kazimierczuk,
M.,
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W.
(1989).
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Hietakangas,
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(2006).
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doi:10.1109/MW-M.2006.247915.
Simo
Hietakangaswas
born
in
Alaha¨rma
¨,
Finland,
in
1980.
He
received
the
M.Sc.
degree
in
Electrical
Engineering
from
the
University
of
Oulu,
Oulu,
Finland,
in
2005,
and
is
currently
working
toward
the
Ph.D.degree
at
the
University
of
Oulu.
His
technical
interests
lie
in
the
field
of
analysis
and
modeling
of
switching
RF
power
amplifiers.
Jukka
Typpo¨was
born
in
Oulu,Finland,
in
1963.
He
received
his
M.Sc.
degree
in
University
of
Oulu,
in
1992,
and
his
Ph.D.degree
in
Norwegian
University
of
Science
and
Technology,
in2003.
Currently,
he
works
as
a
research
fellow
at
Norwegian
University
of
Science
and
Technology,
Department
of
Electronics
and
Telecommunications.
His
current
research
topic
is
integrated
RF
power
amplifiers.
Timo
Rahkonenwas
born
inJyva
¨skyla
¨,
Finland,
in
1962.
He
received
the
Diploma
Engineer,Licentiate,
and
Doctor
of
Technology
degrees
from
the
University
of
Oulu,
Oulu,
Finland,in
1986,
1991,
and
1994,respectively.
He
is
currently
a
Professor
of
circuit
theory
and
circuit
design
with
the
University
of
Oulu,
where
he
conducts
research
on
linearization
and
error-correction
techniques
for
RF
power
amplifiers
and
A/D
and
D/A
converters.
1.6GHZ，2W集成式调谐射频式接收功率放大器的设计
摘要：这篇论文是对一种指定运行在上行频率为1626.5到1660.5MHZ范围内的国际海事卫星集成调谐功率放大器的描述。这个放大器基本的拓扑结构在于并行优化逆E类放大器，修改这类放大器是通过在一个新的位置安装直流隔离电容并且通过调整电容的尺寸来提高低于预期波段频率的稳定性。另外，新的安放位置减少了排水和负载的损失。在电路中很高的电流使得使用宽电感宽度和在芯片上的谐振器的高Q值的手指电容很有必要。该放大器被实现为砷化镓（GaAs）集成电路（IC）的交付2
W的输出功率，而漏极效率为约
56％。测量包括信号源和负载以达到进一步改善该放大器的性能，并在小输入驱动电平进行时调查稳定性。
关键词：逆E级，功率放大器，自激振荡，偏置网络1.介绍在今天的高功率通信系统传统的线性放大器的可用性是由于其低效率而被限制。这个事实推动了向更高效的放大器的研究兴趣，比如E级[1-3]和逆E级[4]。此外，较高的输出功率的需求意味着更高的峰值电流和电压在漏极或集电极电路。这将创建要求高的晶体管的两个最大击穿值和单片微波集成电路（MMIC）的无源电路。有限的导电性和有限的电容大小，以应付热的效果可以通过仔细设计MMIC而达到最小化。另外，晶体管的新兴技术似乎能承受更大的电流密度和峰值电压[5]，因此，在设计高功率器件时，技术的选择变得越来越重要。
本文的目的是要显示与开关高功率射频（RF）功率放大器（PA）具有集成输出脉冲整形的设计经验。在第二章中介绍的E级和逆E级操作是重新审视两种拓扑结构之间的差异.第三章介绍了输入和输出电路，稳定的电路的设计，并提供一些提示关于在一个多指晶体管的输入端减少时差的方式。第四章给出了最终的原理和实现芯片的照片。在第五章中，实测性能是通过使用两个基本的单音测量设备和现代化的负载拉移系统采用多功能调谐器（MPT）进行的报告。最后一个部分提供的有关稳定电路的问题的文章和讨论的摘要。
2.E级与反E级放大器
E级和逆E级被视为开关放大器。理想情况下，在两者的晶体管被驱动打开或关闭，该开关动作产生一系列电压和电流脉冲的输出。这些脉冲相移，因此不会彼此重叠。理想的非重叠将导致晶体管具有100％的漏极效率操作。经典E类漏极波形，归一化到的电源电流和电压的DC值，展示于图1。实线是归一化的漏极电流的波形，虚线是归一化的漏极电压。在E类为最佳操作的要求是零电压开关（ZVS），其中漏极电压和其衍生物变为零，在晶体管导通之前进行。在逆E类的波形已经交换了位置，以便在图1中的实线波形是漏极电压，虚线是漏电流。最佳的操作也被改变到零电流开关（ZCS），其中电流和它的衍生物顺利变为零，在晶体管进入非导通阶段之前。逆E级相对于经典实现的优点是漏极峰值电压比传统的E级较低，在输出电路中的电感值较小，它可以在一个MMIC芯片实现，节省面积，并且通常可以得到更小的电器串联电阻（ESR）[4]。此外，为了接收串联电感作为共振电路的一部分的可能性是有用的，由于寄生电抗可以引起无阻尼共振排出波形[6,7]。这些优势是选择逆E类拓扑结构作为我们研究出发点的原因。然而，调谐的执行不是传统的逆E级，虽然它也有类似的脉冲操作。
3.调谐功率放大器的设计
3.1砷化镓IC工艺
所使用的IC工艺是以TriQuint半导体公司的伪形态高电子迁移率晶体管(pHEMT)
命名的TQPED工艺。该工艺采用增强型和耗尽型场效应两个晶体管（FET）具有0.5lm长光学光刻门，但在我们的例子中，我们只用耗尽型晶体管。可用的耗尽型晶体管具有的27千兆赫的过渡频率（f
t），漏极
-
栅极击穿电压16:05
V和的-0.8V。晶体管的模型中使用标称夹断点是TOM3
FET模型。在这个工业中有其他几个特点：镍铬合金（镍铬）电阻精度和大宗高值电阻，高价值金属
-
绝缘体
-
金属（MIM）电容，1个本地和2层厚度全球金属层[8]。
3.2共振器的设计
在图2中的原始逆E级和在我们的设计中使用的最后调谐的拓扑结构所存在的差别如图3所示，是阻断电容器Cs的位置。在如图2所示的原始的安装提供隔直流分别到两个方向：到输出（负载）
，并且更重要的是，它会阻止直接通过电感Lp的直流电流到地的路径.在我们的情况中，阻塞电容器是在谐振电路的下方如图3所示，其中铯妨碍直流电流流过电感Lp到地，而不是输出（负载）。有一个直接的方法为基本的电流流向输出，而不会传递任何阻塞隔电容器。直流阻塞电容器现在可以被做得更小。在我们的情况中，从100
pF减少到低于50
pF的，这意味着芯片面积节省，并作为辅助效果，能够调整一个稳定的陷阱所需频率（在第三章3.2以上），同时保持良好的放大器的性能。直流阻隔的设计现在也稍微容易些，因为峰值电流流入阻断分支较小。此外，漏极与负载之间的ESR更小了。在Cs元器件中，基波电流振幅各自分别是
1.2和2
A。在图3中可以看出并联谐振器结构的总峰值电流。
传统的逆E类标注[
4
]
的数据是1.6
GHz和功率输出=
3
W导致了较大的芯片面积，因为由于较高的Q
=
10的总电容较大（
63.5
PF）以及
-
由于高的峰值电流（约6
A
）。电感变得巨大。为获得合理的芯片上的元件值的，设计逐渐从[4]中的设计过程将其转向较低负载电阻和Q值，并增加了共振频率。这结束了在一个可提供整齐，不重叠的标注的电流和电压脉冲，合理的尺寸的无源器件，但最终是更接近C级-E基本负荷比原来的逆E类模拟的最终元件值[
9
]用分立元件模型和一个片外低通阻抗匹配网络，以50Ω导致以下尺寸：阻性负载4Ω
，
CTOT
=
30
pF的，电感
LP
=
0:22
NH，并且L很小它可以从最终的设计可以忽略。铯可以降低到50
pF的而不影响整体性能，并且它可以被用来调整一个稳定低于载波陷波，如后面图
8
所示。带有一个大开关晶体管（具有18×50μm/0.5μm手指电容的12个并联的晶体管）估计5.6
W输出功率72％的漏极效率的总的仿真结果。现在面临的挑战是现在要维护良好的输出功率和效率，同时取代（PDK）制程设计套件（PDK）的组件来代替理想的电路元件和同时增加了一些稳定电路的拓扑结构.下一个设计问题与电感的物理设计随之而来。尽管降低Q值的电流幅度仍然如此之高（4.2
A峰值）以至于感应器大概需要200lm宽的金属线，并保持3/4-弯度电感器的中心打开它理论上不能比0.4
nH的小。因此，总的电容和Q值进一步减少了一点，并减少电阻损耗的总电容被分成12并联高Q电容器。谐振器结构的绘制布局导入2.5D场模拟和S参数进行了模拟，并与离散模拟原型进行比较。从S参数模拟比较阻抗数据的卸载相位和幅度都显示在图4和5。分布式谐振器的相位和幅值数据的两个数字被标记以虚线。谐振器的相位和幅度遵循几乎相同曲线。当完整的放大器进行了模拟，漏极效率约为70％，输出功率大概为3.4
W。输出功率的减少可能被解释为由寄生电阻和其他稳定的电路所导致。漏极效率是出乎意料的好，尽管有些降低Q和由经验得到的输出电路设计方式。仿真和实现分布式谐振器如图6所示。3.3
稳定化的放大器
该放大器显示了一种在大信号S参数（LSSP）模拟时不稳定的倾向。最终，稳定必须通过LSSP为基础的稳定的电路里进行评估，因为无条件稳定（K>1）不能没有重大损失来实现。稳定电路被画在整个0.5-5
GHz的频率范围内。经过多次仿真，各种稳定电路必须被用来补偿振铃的性能。首先分立电容器Cs被调谐到50
pF直到生成的输出谐振器的陷大约在1.2千兆赫的频率。这有助于在下面通过罗莱特的K系数在图7所示的频率茅屋频率达到稳定。
50
pF的值被选定既因为输出功率较小的损失又因为有良好的稳定性能。电容器Cs的调谐的影响示于图8，其中电容器被调谐为30?70
pF的范围内。
进一步来说，5Ω的串联电阻被添加到图9（b）所示3的栅极线，以保持放大器稳定范围4.6:1输出驻波比（SWR）。此外，宽频带RC-宿电路被包括在放大器的输入端，以减少在较高频率下的增益。稳定输出SWR范围内的增益的增加而RC滤波器22.6:1。根据模拟的串联电阻引起的约0.46
dB的增益损耗和RC滤波器又是一个额外的0.67分贝。如果放大器必须是无条件稳定（K>1），在0.1千兆赫至8.0千兆赫的频率范围内，串联电阻的增加到9Ω将导致该驱动信号的额外0.40分贝增益损失和更多的衰减。从11.36-9.83分贝的最大增益，然后增益由于稳定的总跌幅降为1.53分贝。在执行仿真的过程中，最大模拟增益为10.23分贝。
3.4一个体积较大的晶体管输入时钟信号
在仿真期间，有广泛的晶体管组成的12918晶体管的每一个为50lm的宽度极端的手指之间有明显的相移。这种相移引起部分重叠输出脉冲之间，降低了漏极效率。此时的输入网络作出示为在图9（a）的例子的阶梯状结构。
FETA和场效应管B之间的线的距离接近1毫米，作为一个纯粹的线延迟将导致大约20
ps的延迟。但在延迟差超过80
ps，同样地输入信号的脉冲宽度是大于预测。由于晶体管不同时切换，他们开始加载对方并消耗较多电能。究其原因，增加了延迟和展宽脉冲宽度是信号依赖的栅极电容，导致在图9（a）未结束的阶梯状输入网络相当数量的二次谐波失真。其中信号路径是几乎相等的长度。改进的时序行为和输入波形相位的模拟是几乎相同的。只是脉冲宽度还是有点大。相等的输入路由增加了放大器的从55漏极效率到68％。栅极电容以及附加解决方案的时序
问题的影响已发表在[10]。4.最终电路该放大器模具尺寸1.96毫米×
3.62毫米（宽×长）被直接粘到6mm厚的铝制散热片。含输出匹配网络和一些栅极偏置网络的镀金印刷电路板（PCB）被安装在散热器上。未来的芯片键合线和SMA连接器被添加到电路中。最终的电路示意图示于图10
，其中虚线是用来分隔上和芯片外组件。左下侧在图中是随后是一个RC宿电路的LC匹配网络。该RC电路提供一个宽带装载在较高的频率增加了放大器的稳定性。在栅极偏置电路，向上从所述匹配电路是并联RLC电路是在工作频率为高阻抗，而片并联RC电路提供了额外的偏置电阻的低频率，因此增加的稳定性放大器。在右侧的晶体管，该调谐输出谐振器与芯片外匹配电路一起被示出。漏极供电电压通过长传输线是在操作频率为高阻抗定向。
在平行的栅极的RC偏置电路和输出匹配电路中的电路板，这简化了实施芯片上实现如图
11所示。左上框（a）是在LC输入匹配，左下框（b）是在RLC偏置网络和对偏置的右侧是包含RC-宿电路的方块（c）所示。的长度相等的输入线都显示在框中（d）中，其中所添加的串联电阻（5Ωeach）显示为宽部分中的相等长度的行之间。晶体管集显示在对话框（E），它由12个晶体管，每个都
包含18手指的每一个为50lm的宽度。晶体管的饱和电流为约4
A.在从晶体管集合右边有输出路径，连同在框中（f）该并联谐振器。焊盘低于（门偏置），左侧（RF中）和高达（RF输出和漏极偏置）。两个或三个接合线，以尽量减少串联电阻和电感，同时最大限度地提高导线输送电流的能力。4.1
所实现的放大器放大器
所实现的放大器在如图12所示与的芯片布局的图像在一起。在实际芯片上，在右侧布置的谐振器结构是清晰可见的。PCB必须钻开和铝基板加工为沿PCB表面平整芯片。这样的接合线被保持尽可能的短。印刷电路板包含由放大器的输出所需要的阻抗变换网络。另外，电源由具有相对高的阻抗在基波和具有低电阻ATDC长线路提供。门偏置网络的一部分也位于PCB上。
PCB的总大小为17.1㎜×37.6毫米。
5.测试性能
5.1测试计划
单音的测量被用来测量放大器的输出功率和效率。一个IFR2025信号发生器和微型电路的缓冲放大器提供25
dBm的驱动信号电平。输出是由一个罗德与施瓦茨ZVA8矢量频谱分析仪（VSA）测量。
负载牵引测量进行与该均被施加到放大器的输入和输出聚焦微波MPT1820调谐器。作为一个来源是罗德与施瓦茨公司的SMU200A带缓冲放大器。输入功
率水平分别为15?25
dBm的。
RF输入和输出功率测量与安立ML2438A功率测定仪，双输入。频谱和振荡尖峰谐波含量测定与Rohde＆Schwarz公司的FSQ40
VSA。
5.2调谐放大器
在所述第一测量放大器不符合仿真响应。测量只有0.96
W的输出功率在1575
MHz这时仿真的的数字分别为3.4
W的输出功率和漏极效率为70％，所有的电压源为5.5
V。我们怀疑电源电压指向该传递非常接近输出划线谐振器结构并且可能耦合输出到放大器的输入端。划线切割用紫外线激光，但这必须测量放大器的直流电流的频率相应。没有结果比模拟高的，这表明在开关级的负载阻抗太低。看到在漏阻抗增加了更换一对2.7
pF的高Q值陶瓷电容（放大器A，在表1）在外部输出网络与一个2.9
pF电容匹配（放大器B，在表1）。该变形增大了输出功率为2瓦并且漏极效率到56％在625兆赫的频率下。输出功率和频率范围内的1.5-1.7
GHz的效率示于图13。输出功率保持在0.53分贝在所需的频率范围（1626.5-1660.5兆赫），如图13所示。保持相同频带的漏极效率保持53％之上，而最高效率，56％，达到了1626兆赫。
通过调节供电电压，放大器的效率可以进一步增加，这可以从图14中可以看出。当供电电压降低，漏极效率稳步上升。在2.5
V和1625
MHz的频率的电源电压时，放大器具有65％的漏极效率。这意味着该放大器可以保持高效的操作也以包络消除与恢复（EER）的系统中使用时。峰值电压在最低的电源电压图
14归根于输出信号驱动信号馈通。5.3负载迁移的测试
测量了负载拉移系统在1.6GHz的频率点进行，以几个修改放大器。放大器之间的差异显示在表一.接下来的章节中，我们将主要集中在放大器C和D，其原因是显而易见以后。现在让我们讨论放大器C这是非常相似的放大器B早期测量。负载拉移系统的调谐器被连接到放大器C的输出和输入的基波，二次谐波和三次谐波的负载调谐导致约2.4W的输出功率（33.8dBm的），同时保持约57.4％效率在这个峰值功率点。
在电力方面的基本负载阻抗是在比最佳的漏极效率点稍高的阻抗如图15所示，其中-1分贝输出功率点（三角形）和-5％单元的效率点（圆圈）被示出。图中的峰值效率点为（a）（58.6％）和峰值功率是（B）（33.9
dBm的）。最佳效率区域是相当大的。两个负载谐波甚至更放松，并且有在输出功率为实施例的区别被测定为分贝的十分之一，而不是分贝。另外，在效率差异，测定在一个或两个百分比单位代替五到十。作为一个例子，在第三谐波最佳输出内0.2分贝从2％以内的单位从最大（圆圈）最大（三角形）和效率分点被显示在图16。因为它可以被看见，三次谐波的阻抗不是至关重要的，因为基本音的最佳效率是标有（a）和最大输出功率是标有（b）所示。应当指出的是，三次谐波的调整并没有增加的绝对尺度也不漏极效率的输出功率。峰值输出功率值保持在基本负载牵引和漏极效率峰值在
0.2dB仅仅从上升从58.6％59.8％在图16的史密斯圆图（a）点所示。
放大器谐波调谐的不敏感性是由长漏极偏置线在第二谐波的低阻抗和低通匹配网络在该衰减的三次谐波的输出引起的。
5.4
元的迁移测量
根本阻抗源拉并提高输出功率和放大器?稍微的效率。最佳的漏极效率（圆圈）和输出功率点（三角形）
（
a）和（
b）中，分别示出图
17
。电源点的范围内的2
％为单位的差0.2分贝和效率的限制内。该放大器效率提高的根本源泉调整至62.1
％
（点）和输出约2.5瓦（
34.1
dBm时，
b点）
。谐波源拉测量结果表明，谐波阻抗是不一样重要的基础。这是由于在低通输入匹配和宽带RC-宿电路。在RC
-宿电路降低了阻抗，尤其是在高频率所计算的幅度，如图18（
b）所示。这具有的效果既二次和三次谐波的阻抗。未经RC-漏极的阻抗的大小如图18中的（
a）所示。在这两种情况下的输入匹配电路不包括在计算中。5.5放大器的稳定性
起初放大器A确实显示了一些不稳定的行为而引起的不足去耦偏置在漏极电压调制。不稳定出现在低输入功率水平的噪声边带就是骗基频的两侧。当输入功率被进一步下调时，放大器也打入全面振荡。作为治疗，电源阻抗是由大量的去耦电容（4×470
PF）的降低加到漏。在能效比应用中，电源调制器将提供足够低的阻抗在漏级。
当负载拉做是为了在放大器A，C和D中，寄生振荡的检测是在-50
dBc的水平施加。采用这种设置，我们能够不同放大器的灵敏度进行比较振荡。我们发现，对RC-宿电路用在放大器A和C确实改善的稳定性，尤其是在低输入功率水平。用于比较的数据被从放大器D，其中对RC-漏极用紫外线激光切割测定。用低15
dBm的输入功率基本阻抗负载牵引的振荡点示于图19。振荡边带检测are1701和1489兆赫。如果我们比较该结果到放大器A，发现振荡点的数量是相当小的，并将它们的位置是相当紧密间隔在低阻抗区域中，如图所示
20。在这种情况下，振荡频率为1568兆赫。放大器A和放大器D在调制虚拟原件上有一些不同：无阻尼电路的虚拟调制频率约为±100兆赫，然而当存在阻尼时的调制出现在大约±30兆赫。对于这一现象的可能的原因是不同的漏级旁路当放大器D有比较的少供应电容（4×470
pF或更少）。通过从输入到加载传输（S21）中的漏极偏压和匹配网络来研究这个现象的影响。放大器D中的电路显示出了谐振大约93兆赫时的反应，如图21（a），而在放大器A的漏极共振是27
MHz的频率，如图21（b）所示所示。作为参考，放大器A的输出的测定光谱示于图22，其中标记物1和四个正处于从基频±33兆赫的距离也在该图中。在这种情况下输入功率是15
dBm并且基本负载阻抗是在被发现振荡阻抗之一（Г=0.370，O
=165.3）。芯片的去耦电容（4×470
pF的）在放大器A的情况下的增加降低了大约在100兆赫到30兆赫区域做共振时反应。在±30
MHz频段之内也有其它类似于一个准周期解决方案和准周期和混沌的光谱的组合。例如准周期和混沌光谱[11]显示。看到了共振的一个有趣的问题是，由于其高的电感系数，施加到偏置供应上的大型电解电容器没有减弱大约30
MHz的共振。5.6额外的发现
开关放大器依赖于栅极驱动器足够的数量，并且各种各样的的驱动信号快速地影响放大器的性能。在我们的例子中晶体管的夹断电压的微小变化导致2-3分贝时的增益的差别在放大器之间，这时电压保持在恒定。这种明显的差异可以被发现在矢量网络分析仪测量了0
dBm的输入驱动时。更加恒定的结果可以被推断通过调节微小的漏极偏置电流相等时，没有驱动信号被施加而得到。现在增益的测量结果在0.8分贝以内匹配。6.总结
一个调谐射频（RF）功率放大器已经被设计用于在一个1.6-1.7
GHz范围的频带上操作。放大器根据经验的设计具有非重叠的漏极电压和电流脉冲，并且所要求的谐振电路已经在芯片上应用。阻隔直流电容器的一个新的位置会产生谐振陷阱，这个谐振陷阱是用于使放大器稳定在低于所需频带的范围内，和一个栅极的
RC-宿电路被用于稳定放大器使之工作在一个在较高频率内。另外，长度相等的输入线实施了以时钟门信号。
放大器的稳定性是通过对大信号S参数和稳定圆模拟评价得来的。附加电阻与RC-宿电路一起不得不被施加，以保持输出SWR在超过22.6:1的稳定。放大器被应用到一个GaAs衬底具有耗尽型高电子迁移率晶体管（FET上。已被应用的放大器提供输出功率为2瓦，同时保持56％的漏极效率。频率响应是0.53分贝之内在一个频带为1626.5-1660.5兆赫的范围内，而漏极效率保持在高于53％的期望的频带内。
在1.6
GHz的一个频率上也对放大器测量了负载牵引系统。在调谐器放大器的帮助下实现了输出功率约为2.5
W以及62％的效率。负载牵拉还与在小驱动电平时放大器的灵敏度振荡程度有关。有人发现，输出匹配网络具有可能导致不稳定的表现低频共振。被实行的门下沉被验证用于稳定电路。
它可能是一个有益的想法来设计调谐到第二谐波的输入LC-陷波电路中，由于存在于该加宽的输入波形在时域上，在效率和功率方面产生问题当输入为第二谐波时。进一步，增加了第三谐波含量可能使输入波形的变得更加趋于方形，这是在开关放大器所希望的特征。
感谢：这篇论文得到了
The
Academy
of
Finland,
Infotech
Oulu
Graduate
School,
TriQuint
Semiconductor
Inc.,
Nokia
Foundation,
Tauno
Tonning
Foundation,Ulla
Tuominen
Foundation
and
The
foundation
of
Riitta
and
Jorma
J.
Takanen的支持。对
the
Department
of
Electronics
and
Telecommunications
in
the
Norwegian
University
of
Science
and
Technology
(NTNU)
and
to
the
personnel
of
the
Micro-
and
Nanotechnology
Centre
in
the
University
of
Oulu.表示由衷的感谢
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Simo
Hietakangaswas
born
in
Alaha¨rma
¨,
Finland,
in
1980.
He
received
the
M.Sc.
degree
in
Electrical
Engineering
from
the
University
of
Oulu,
Oulu,
Finland,
in
2005,
and
is
currently
working
toward
the
Ph.D.degree
at
the
University
of
Oulu.
His
technical
interests
lie
in
the
field
of
analysis
and
modeling
of
switching
RF
power
amplifiers.
Jukka
Typpo¨was
born
in
Oulu,Finland,
in
1963.
He
received
his
M.Sc.
degree
in
University
of
Oulu,
in
1992,
and
his
Ph.D.degree
in
Norwegian
University
of
Science
and
Technology,
in2003.
Currently,
he
works
as
a
research
fellow
at
Norwegian
University
of
Science
and
Technology,
Department
of
Electronics
and
Telecommunications.
His
current
research
topic
is
integrated
RF
power
amplifiers.
Timo
Rahkonenwas
born
inJyva
¨skyla
¨,
Finland,
in
1962.
He
received
the
Diploma
Engineer,Licentiate,
and
Doctor
of
Technology
degrees
from
the
University
of
Oulu,
Oulu,
Finland,in
1986,
1991,
and
1994,respectively.
He
is
currently
a
Professor
of
circuit
theory
and
circuit
design
with
the
University
of
Oulu,
where
he
conducts
research
on
linearization
and
error-correction
techniques
for
RF
power
amplifiers
and
A/D
and
D/A
converters.
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